Yup, the ADU count-down/count-up is Sony's approach, but it is tightly integrated into their column-parallel ADCs. Instead of handling digital CDS off-die, for example, Sony simply integrates it directly into the ADC for each column. Reset count is negative, exposure count is positive, with the offset correcting the noise contribution from dark current present at sensor reset time. Concurrently, the specific approach to CP-ADC Sony uses cancels out banding via fine tuning each ADC (or maybe it is simply because they have an ADC per column, and the benefit is by default, as I have yet to find any patent directly describing how they cancel banding), which is how they correct banding. There is a nice PDF that explains it all...and I have the link...I'll go dig it up...
Here we go. Sony's CP-ADC paper. Seems there are two things that reduce banding. According to the paper, the use of analog CDS circuitry is itself the cause of some horizontal banding, due to variations in CDS circuits per pixel:
Also a capacitor with a size larger than a certain value is required in the CDS circuit...
(text cut, se previous post)
Additionally, Sony's CP-ADC, since it is low-frequency thanks to being per-column, allows them to eliminate high-frequency contributors to signal noise in the A/D conversion and Digial CDS unit:
Another advantage of the column-parallel A/D converter technique lies in its conversion speed. Since processing is performed in parallel for each column, the A/D conversion frequency is extremely low, and the high-frequency band noise components can be separated from the signal components.
For those who are interested in the exact process of A/D conversion and digital CDS in Sony's CP-ADC approach, here it is:
The column-parallel digital CDS technique operating sequence is as follows.
(text cut, se previous post)
The "low frequency" you're referring to is all due to the number of AD converters used. There's nothing advanced or even remotely "patentable" about this. The signal frequency in a readout is:
[# of pixels * ops per frame * fps] divided by [numbers of AD units used]
In a per-column system you get [the numbers of columns] AD-converters, in a normal ~20MP sensor that's about 6000. Many off-sensor AD systems use between 4-16 (Canon use 8-16, 5Dmk3 uses a 2x4channel setup and the 1Dx uses 4x4channels). That gives a (6048 / 2 / = 400x lower quantization frequency if we assume that both are 14-bit and have the same fps. Quantization noise typically rises asymptotically with frequency above a certain point. Aptina have some systems with AD-on-chip that uses one for each 12 columns or some number close to that, giving about 400 AD converters per system. There are and cannot be any patents regarding how many AD converters per row or column you use.
I never said there was. The patents are for the design of the ADC/CDS units, not their frequency. The point is that *part* of that design involves keeping high-frequency components (i.e. the core PLL clock) out of the ADCs so they don't introduce high frequency banding.
To get rid of almost 100% of the banding effect, you just have to make sure that the response from each of the AD converters is the same as the others. Toshiba's effort in the 5200 sensor shows what you can achieve just by keeping a good control over your manufacturing process - since they don't use any kind of column-balancing strategy what so ever, except for the prerecorded dark frame on the Fujitsu made EXPEED chip - according to the die SEMs I've seen. So they show how well you can balance 6080 AD converters without any fancy processing, why can't Canon balance 8?
First, the Toshiba chip still has some banding, and its been enough to make customers complain. If we are talking 100% elimination here, so far, the only sensor I know that does that is Exmor.
According to the PDF, you don't need to actually balance anything. That is why I think it is rather elegant...according to Sony themselves, they eliminated circuitry
, and moved circuitry around
, to produce a low-noise environment for ADC
. The simple nature of column-parallel
ADC with digital CDS
IS the solution to the problem. It is a very elegant, simple solution to the problem...that is what I love about it, and why I don't think it will be a breeze for Canon to reproduce. I thought there was some per-ADC fine tuning, but the sources of banding noise are the analog CDS circuitry itself (horizontal, thanks to transistor variance) and high frequency components in the ADCs (vertical, we all know about this). The very act of moving to CP-ADC (verses column-bucket parallel ADC like Toshiba) is what eliminates both forms of banding noise, effectively "for free".
To increase the performance at lower ISOs, where the off-die electronics add in more noise than the on-die electronics in all Canon cameras - increase the quality of the off-chip electronics and fix the signal layout problems. This isn't very hard to do either - if you WANT to do it.
I wouldn't call the quality of Canon DIGIC chips low. They are very high quality components already. They are also very high frequency components...high frequency, a major source of banding. Combine that with the use of analog CDS, which thanks to variance in the CDS transistors, causes horizontal banding, plus the high frequency bus to ship the analog sensor off the sensor die to those DIGIC chips...
Seems the trend of moving all of these components onto the sensor die and increasing parallelism is solving a lot of noise problems in and of itself. I don't think Canon is simply ignoring the problem...they aren't some evil corporation giggling gleefully as they watch their customers bleed cash. They have a transistor size problem, 500nm is showing its age. I think Canon can easily fix that, they have already demonstrated 180nm technology. I think now it is a matter of moving all that off-die junk onto the sensor die and increasing parallelism, and going digital. If they skip the digital part, I think things will definitely improve, but I doubt they will match Exmor in total quality.
On-chip electronic noise is indeed very important at higher ISOs, just think about it. At ISO6400 you have ~64x less photons available than at base ISO, in a 5Dmk3 that makes about 1000e- per pixel give pure white. -4Ev, i.e slightly darker than middle gray is 16x lower than white: 1000/16 = 62 e-. The inherent noise in that gray is sqrt(62) = 8e-.
Now, compared to the 8e- of natural light noise, having 1e- or 10e- in added electronic noise makes quite a difference. Since Canon sensors have a very good on-chip CDS, they have a read noise of about 3e-. That's almost exactly the same as in the D800 sensor.
Sure, the same as the D800 sensor at all ISO settings
. I guess I don't see why the D800 having 2.6e- at ISO 6400 is a major contributor to noise when the 5D III has 2.9e-, and according to the review the 5D III seems to do better at high ISO settings than the D800. Noise at those ISO levels is so completely dominated by photon noise that the contribution from electronic noise is effectively meaningless.Getting back on-topic.
Canon has mentioned they have some new noise-reduction technology they have employed in the high-MP sensors floating around in prototype cameras. I don't know of any of that noise-reduction technology is on-die ADC and NR, but there was at least a rumor that they were using active thermal cooling which resulted in very low read noise. Sounds like that may take care of more dark current noise (which is usually what extreme cooling is employed for), however I don't know if that will address the issue of off-die ADC noise. I'm not sure a "little bit of balancing" will do much either...DIGIC is a high quality chip designed by Canon and manufactured at high quality fabs on modern processes. Canon may be able to reduce the 40mp sensor's contribution to read noise well below the 1e- mark with adequate active cooling, but will that take care of the worse offender....banding noise?