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Author Topic: Canon Dual-Scale Column-Parallel ADC Patent  (Read 7182 times)

TheSuede

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Re: Canon Dual-Scale Column-Parallel ADC Patent
« Reply #45 on: December 22, 2013, 01:05:48 PM »
The patent is old and probably conceptually invalid due to prior-art. And I'm pretty surprised about the confusion about what it does, as it's fairly straight-forward and easy to read.

What Canon patented here is a specific implementation, not a method, of a two-stage pre-selection of AD reference voltage.

As the signal is presented to the AD section, the absolute voltage is first presented to a comparator circuit. In the "determination period" the comparator sets the AD ramp signal to either a high (fast) reference ramp, or a low (slow) reference ramp.

If the signal is (was) lower than the comparator set point, then the AD works with a slower ramp and after that it scales the result down numerically by a factor of [high ramp] / [low ramp]. This enables a "slower" readout of weak signals, something which offsets the crappy (noisy) AD converters base level noise for low-level signals. Signals stronger than the comparator set point will be digitized with lower precision, but in strong signals that inaccuracy is totally dominated by photon shot noise.

If you use higher quality AD converters or a slower bitrate conversion this two stage setup is not necessary. Often slower reads are implemented by higher parallelism, using more AD converters per image. This is what Sony's Exmor, or indeed any other of the five big one's on-sensor AD conversions. They use the "slow ramp" for all pixels, all the time, anyway.

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Re: Canon Dual-Scale Column-Parallel ADC Patent
« Reply #45 on: December 22, 2013, 01:05:48 PM »

CarlTN

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Re: Canon Dual-Scale Column-Parallel ADC Patent
« Reply #46 on: December 26, 2013, 03:26:41 PM »
They aren't splitting it. I am not 100% exactly certain what they are doing, but from what I do understand, when a pixel is read, it is amplified twice, and the results of those different amplifications are transferred to the CP-ADC units simultaneously (on different channels). Same source pixel, two separate but full power signals, which are then blended together at conversion time. It is basically the same thing ML did, only with the appropriate dedicated hardware fabricated right into the sensor to do it right.

I assume there is something clever somewhere in the implementation. HDR has been around for a while, even before ML. It's hard to believe nobody thought earlier about pushing the process into the sensor instead of software.

I wouldn't call it HDR. HDR is a very misused term as it is. In its proper form, a High Dynamic Range image is an image with an EXCESSIVBLY HIGH dynamic range, stored as 32-bit floating point numbers with extremely fine precision and a dynamic range that could potentially equal thousands of stops (i.e. it can represent numbers from a couple billion down to billionths.)

HDR as it is commonly (mis)used simply refers to the mapping of tones into a limited dynamic range from a source file that might have slightly higher dynamic range. What Canon is doing isn't exactly HDR...it is a specialized read process that will allow them to better utilize the dynamic range they already have access to, but which is otherwise being diminished by read noise.

Nice concise explanation...

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Re: Canon Dual-Scale Column-Parallel ADC Patent
« Reply #47 on: December 26, 2013, 06:41:50 PM »
The patent is old and probably conceptually invalid due to prior-art. And I'm pretty surprised about the confusion about what it does, as it's fairly straight-forward and easy to read.

What Canon patented here is a specific implementation, not a method, of a two-stage pre-selection of AD reference voltage.

As the signal is presented to the AD section, the absolute voltage is first presented to a comparator circuit. In the "determination period" the comparator sets the AD ramp signal to either a high (fast) reference ramp, or a low (slow) reference ramp.

If the signal is (was) lower than the comparator set point, then the AD works with a slower ramp and after that it scales the result down numerically by a factor of [high ramp] / [low ramp]. This enables a "slower" readout of weak signals, something which offsets the crappy (noisy) AD converters base level noise for low-level signals. Signals stronger than the comparator set point will be digitized with lower precision, but in strong signals that inaccuracy is totally dominated by photon shot noise.

If you use higher quality AD converters or a slower bitrate conversion this two stage setup is not necessary. Often slower reads are implemented by higher parallelism, using more AD converters per image. This is what Sony's Exmor, or indeed any other of the five big one's on-sensor AD conversions. They use the "slow ramp" for all pixels, all the time, anyway.

Thanks for the explanation! Basically what it sounded like, but I couldn't figure out the exact mechanism by which they reduced noise. Slower readout for lower signals makes total sense. Sorry, I was reading a rather poor translation from japanese...god awful ass-backwards sentences and funky wording.
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Re: Canon Dual-Scale Column-Parallel ADC Patent
« Reply #47 on: December 26, 2013, 06:41:50 PM »