If you are assuming they use a single mask in a single exposure to generate an entire wafer of sensors, then you would be incorrect.
No, a single mask per pass (exposure)
of the entire wafer.
Remember that the whole point of using a mask and deep or extreme ultraviolet light wavelengths is that it allows the mask to be orders of magnitude larger than the actual CMOS device being fabricated. Were talking many thousands to millions of times larger...macro scale vs. nano scale.
I think you're off a bit. According to Wikipedia and other sources, masks typically use 4x magnification (even for EUVL), or on occasion, 8x or 10x. Certainly not millions of times larger.
With that said, apparently I'm somewhat out of date. The older chip manufacturing did typically expose an entire wafer at once, but apparently that isn't practical these days. My bad. Either way, my main point still remains that you can lay out arbitrary patterns of chips on the wafer.
Also, I'm not sure rotation would really be as hard as you think. Assuming a square mask, you could readily produce a second mask with the pattern rotated 90 degrees, and use that mask when exposing the additional bits. It shouldn't matter that part of the projected area is outside the bounds of the wafer. Then, after you cut the wafer, it shouldn't take that
much effort to rotate a few of the parts 90 degrees as they're moved from the sliced wafer to wherever the next step in manufacturing occurs. Once you've done that, the remainder of your process can treat those parts the same as the other parts.
With that said, the more masks you build, the higher your overhead, so that approach probably wouldn't be nearly as efficient cost-wise as filling in the wasted parts of the wafer with smaller chips that you have to make anyway.