I got bored at work so made some drawings on CAD:

Take an 8" wafer (radius 101.6mm).

Take a 7D-sized sensor (22.3*14.9mm), add 5% to each size to account for bits around the edge and cutting and whatnot, makes 23.415*15.645 per sensor.

Draw them out, you get 4 rows of 8 wide in the middle, plus 2 rows of 6, 1 of 4 and 1 of 2 each side, I get 68 APS-C sensors from an 8" wafer.

Take a 5D3-sized 36*24mm, add 5% to each side again, you get 37.8*25.2. Laying them out I get 24 sensors (5 rows of 4 plus 2 top and bottom).

So that's theoretically 2.8x better. Can't muck around too much at work, so i'm not going to do 12".

As for yields, i dunno. Deposit 5 defects around the wafer, you might hit 5 of the aps-c sized sensors, but you might only hit 4 of the FF sensors (one could get hit twice). Still, knock 5 out of each and you get 19 FF or 63 APS-C, now we're at 3.3x more chips per wafer.