Canon Dual-Scale Column-Parallel ADC Patent
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unfocused said:
I don't think you're correct on this ML prediction.
If you've tried a Olympus EM1 you'll see just how responsive and useful a good ML-EVF system can be and the tech's got some legs yet.
I don't think ML will "run its course." It will become an alternative to the traditional SLR type camera body. Each will have their pros and cons and appeal to different consumer segments.
All the MFT cameras and Fuji's higher end bodies are proving they're very capable already. It will only be a matter of another generation or 2 before they will likely outperform even the best DSLRs for shooting speed, both AF and fps.
Higher frame-rate EVFs with higher resolution will surely arrive though they're already adequate to rival optical VFs for functionality. Battery drain will be improved, extending their operating duration. These advances may even arrive from the traditional SLR mfrs first. I'm sure they can see the foreshadowing such technology is having on them. PentNikCan have already ventured into ML categories, not very successfully, but they've gotten their toes wet and will have to continue and may even have to get competitive, at least in their own way, within the next couple years.
The future WILL carry on WITH mirrorless cameras. The end-of-times for glass-flappers is nigh.
And I welcome the advantages it will bring.
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UPDATE
So, I've read through most of the patent's embodiments now. I am not sure that this is actually similar to what ML did. I do think it has to do with noise reduction, however it achieves it in a different way. From what I understand, this patent uses two signals of different ADC "precision", in comparison with the source pixel signal, and a set of circuitry to increase ADC speed, increase ADC accuracy, while maintaining a constant load level despite changing voltages.
The "constant load level" is what intrigued me the most. I believe it is a varying load level in Canon's current ADCs that leads to a bulk of their read noise. When load varies in an electrical circuit, it creates oscillations..."noise", a good example of which would be that electrical buzz in a DC circuit. If you can maintain a constant load, your noise level will drop considerably.
So, while this might not be as interesting as a Magic Lantern-style dual ISO read, I think it would still have the same effective result: Less read noise, more dynamic range at low ISO. The use of reference signals at different voltage ramps is simply to provide a secondary source for comparison with the actual pixel clock, and the option to select the more accurate signal...it really doesn't have anything to do with Dual ISO. I suspect that if Canon ever does pursue Dual ISO, the patent would probably refer more directly to such a mechanism...this patent only really directly referred to high and low precision ADC, constant load, and higher ADC accuracy...none of which really seemed to indicate ISO to me.
So, I've read through most of the patent's embodiments now. I am not sure that this is actually similar to what ML did. I do think it has to do with noise reduction, however it achieves it in a different way. From what I understand, this patent uses two signals of different ADC "precision", in comparison with the source pixel signal, and a set of circuitry to increase ADC speed, increase ADC accuracy, while maintaining a constant load level despite changing voltages.
The "constant load level" is what intrigued me the most. I believe it is a varying load level in Canon's current ADCs that leads to a bulk of their read noise. When load varies in an electrical circuit, it creates oscillations..."noise", a good example of which would be that electrical buzz in a DC circuit. If you can maintain a constant load, your noise level will drop considerably.
So, while this might not be as interesting as a Magic Lantern-style dual ISO read, I think it would still have the same effective result: Less read noise, more dynamic range at low ISO. The use of reference signals at different voltage ramps is simply to provide a secondary source for comparison with the actual pixel clock, and the option to select the more accurate signal...it really doesn't have anything to do with Dual ISO. I suspect that if Canon ever does pursue Dual ISO, the patent would probably refer more directly to such a mechanism...this patent only really directly referred to high and low precision ADC, constant load, and higher ADC accuracy...none of which really seemed to indicate ISO to me.
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The patent is old and probably conceptually invalid due to prior-art. And I'm pretty surprised about the confusion about what it does, as it's fairly straight-forward and easy to read.
What Canon patented here is a specific implementation, not a method, of a two-stage pre-selection of AD reference voltage.
As the signal is presented to the AD section, the absolute voltage is first presented to a comparator circuit. In the "determination period" the comparator sets the AD ramp signal to either a high (fast) reference ramp, or a low (slow) reference ramp.
If the signal is (was) lower than the comparator set point, then the AD works with a slower ramp and after that it scales the result down numerically by a factor of [high ramp] / [low ramp]. This enables a "slower" readout of weak signals, something which offsets the crappy (noisy) AD converters base level noise for low-level signals. Signals stronger than the comparator set point will be digitized with lower precision, but in strong signals that inaccuracy is totally dominated by photon shot noise.
If you use higher quality AD converters or a slower bitrate conversion this two stage setup is not necessary. Often slower reads are implemented by higher parallelism, using more AD converters per image. This is what Sony's Exmor, or indeed any other of the five big one's on-sensor AD conversions. They use the "slow ramp" for all pixels, all the time, anyway.
What Canon patented here is a specific implementation, not a method, of a two-stage pre-selection of AD reference voltage.
As the signal is presented to the AD section, the absolute voltage is first presented to a comparator circuit. In the "determination period" the comparator sets the AD ramp signal to either a high (fast) reference ramp, or a low (slow) reference ramp.
If the signal is (was) lower than the comparator set point, then the AD works with a slower ramp and after that it scales the result down numerically by a factor of [high ramp] / [low ramp]. This enables a "slower" readout of weak signals, something which offsets the crappy (noisy) AD converters base level noise for low-level signals. Signals stronger than the comparator set point will be digitized with lower precision, but in strong signals that inaccuracy is totally dominated by photon shot noise.
If you use higher quality AD converters or a slower bitrate conversion this two stage setup is not necessary. Often slower reads are implemented by higher parallelism, using more AD converters per image. This is what Sony's Exmor, or indeed any other of the five big one's on-sensor AD conversions. They use the "slow ramp" for all pixels, all the time, anyway.
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TheSuede said:
Thanks for the explanation! Basically what it sounded like, but I couldn't figure out the exact mechanism by which they reduced noise. Slower readout for lower signals makes total sense. Sorry, I was reading a rather poor translation from japanese...god awful ass-backwards sentences and funky wording.
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